// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`define CPU_GLOBAL_MAX_ADDR             20           // CPU Global CSR
`define CPU_PFR_MAX_ADDR                15          // CPU PFR CSR

/*************************************************************************************************************
 * CSR Address Offset                                                                                        *
 *************************************************************************************************************/
`define MAIN_FPGA_VERSION_ADDR          16'h00
`define MAIN_REV_CTRL_ADDR              16'h04
`define MAIN_BUILD_TIME_ADDR            16'h08
`define MAIN_BUILD_CATEGORY_ADDR        16'h0C
`define MAIN_DEVICE_LOCATION_ADDR       16'h10
`define MAIN_STATUS_ADDR                16'h14
`define MAIN_SCRATCH_ADDR               16'h18
`define CPU_PWR_SEQUENCE_STATUS_ADDR    16'h1C
`define CPU_PWR_SEQUENCE_CONTROL_ADDR   16'h20
`define CPU_GLBRST_FLOW_CONTROL_ADDR    16'h24
`define CPU_ADR_COUNTER1_ADDR           16'h28
`define CPU_ADR_COUNTER2_ADDR           16'h2C
`define CPU_NMI_SELECTOR_IRQ            16'h30
`define CPU_DEBUG_PWR_SEQUENCE_1        16'h34
`define CPU_DEBUG_PWR_SEQUENCE_2        16'h38
`define CPU_DEBUG_PWR_SEQUENCE_3        16'h3C
`define CPU_DEBUG_PWR_SEQUENCE_4        16'h40
`define CPU_DEBUG_PWR_SEQUENCE_5        16'h44
`define CPU_DEBUG_PWR_SEQUENCE_MULT_SEL 16'h48
`define CPU_DEBUG_PWR_SEQUENCE_POINTER  16'h4C

/*************************************************************************************************************
 * CSR Default Value                                                                                         *
 *************************************************************************************************************/
`define MAIN_BUILD_CATEGORY_DEF         01'h0       // Clean Build
`define MAIN_DEVICE_LOCTAION_DEF        02'b10      // Main FPGA Location